[Pcre-svn] [997] code/trunk: Improved instruction cache flus…

Revision: 997

          http://vcs.pcre.org/viewvc?view=rev&revision=997
Author:   zherczeg
Date:     2012-07-27 12:31:03 +0100 (Fri, 27 Jul 2012)

Log Message:
-----------
Improved instruction cache flush for POWER/PowerPC

Modified Paths:
--------------
    code/trunk/ChangeLog
    code/trunk/sljit/sljitConfigInternal.h
    code/trunk/sljit/sljitNativePPC_common.c

Modified: code/trunk/ChangeLog
===================================================================
--- code/trunk/ChangeLog    2012-07-12 10:10:51 UTC (rev 996)
+++ code/trunk/ChangeLog    2012-07-27 11:31:03 UTC (rev 997)
@@ -22,7 +22,10 @@
     atomic brackets at the start of a pattern, or where there was a subsequent 
     *PRUNE or *SKIP.

+7.  Improved instruction cache flush for POWER/PowerPC.
+    Patch by Daniel Richard G.

+
Version 8.31 06-July-2012
-------------------------

Modified: code/trunk/sljit/sljitConfigInternal.h
===================================================================
--- code/trunk/sljit/sljitConfigInternal.h    2012-07-12 10:10:51 UTC (rev 996)
+++ code/trunk/sljit/sljitConfigInternal.h    2012-07-27 11:31:03 UTC (rev 997)
@@ -93,9 +93,9 @@
 #else
 #define SLJIT_CONFIG_ARM_V5 1
 #endif
-#elif defined(__ppc64__) || defined(__powerpc64__) || defined(_ARCH_PPC64) || (defined(_AIX) && defined(__64BIT__))
+#elif defined(__ppc64__) || defined(__powerpc64__) || defined(_ARCH_PPC64) || (defined(_POWER) && defined(__64BIT__))
 #define SLJIT_CONFIG_PPC_64 1
-#elif defined(__ppc__) || defined(__powerpc__) || defined(_ARCH_PPC) || defined(_AIX)
+#elif defined(__ppc__) || defined(__powerpc__) || defined(_ARCH_PPC) || defined(_ARCH_PWR) || defined(_ARCH_PWR2) || defined(_POWER)
 #define SLJIT_CONFIG_PPC_32 1
 #elif defined(__mips__)
 #define SLJIT_CONFIG_MIPS_32 1

Modified: code/trunk/sljit/sljitNativePPC_common.c
===================================================================
--- code/trunk/sljit/sljitNativePPC_common.c    2012-07-12 10:10:51 UTC (rev 996)
+++ code/trunk/sljit/sljitNativePPC_common.c    2012-07-27 11:31:03 UTC (rev 997)
@@ -40,24 +40,37 @@
 static void ppc_cache_flush(sljit_ins *from, sljit_ins *to)
 {
 #ifdef _AIX
-    _sync_cache_range((caddr_t)from, (size_t)(to - from) * sizeof(sljit_ins));
-#else
+    _sync_cache_range((caddr_t)from, (int)((size_t)(to - from) * sizeof(sljit_ins)));
+#elif defined(_ARCH_PWR) || defined(_ARCH_PWR2)
+    /* Cache flush for POWER architecture. */
     while (from < to) {
-#if defined(__GNUC__) || (defined(__IBM_GCC_ASM) && __IBM_GCC_ASM)
-        __asm__ volatile ( "icbi 0, %0" : : "r"(from) );
+        __asm__ volatile (
+            "clf 0, %0\n"
+            "dcs\n"
+            : : "r"(from)
+        );
+        from++;
+    }
+    __asm__ volatile ( "ics" );
+#elif defined(__GNUC__) || (defined(__IBM_GCC_ASM) && __IBM_GCC_ASM)
+    /* Cache flush for PowerPC architecture. */
+    while (from < to) {
+        __asm__ volatile (
+            "dcbf 0, %0\n"
+            "sync\n"
+            "icbi 0, %0\n"
+            : : "r"(from)
+        );
+        from++;
+    }
+    __asm__ volatile ( "isync" );
 #ifdef __xlc__
-#warning "This file may fail to compile if -qfuncsect is used"
+#warning "This file may fail to compile if -qfuncsect is used."
 #endif
 #elif defined(__xlc__)
 #error "Please enable GCC syntax for inline assembly statements with -qasm=gcc"
 #else
-        /* Power equivalent of icbi, not used yet. */
-        /* __asm__ volatile ( "clf 0, %0" : : "r"(from) ); */
-
 #error "This platform requires a cache flush implementation."
-#endif
-        from++;
-    }
 #endif /* _AIX */
 }